H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024
Public

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B.5.13. Higher 2 bytes of the Destination address for Flow Control

Offset: 0x60E

Higher 2 bytes of the Destination address for Flow Control Fields

Bit Name Description Access Reset
15:0 daddrh Flow control Destination Address
Upper 2 bytes of the 6 byte destination address used for SFC and PFC frames
  • At power-on, daddrh is set to 16'h0180
  • After i_csr_rst_n is asserted, daddrh is set to the value given by module parameter tx_pause_daddr[47:32]
RW 0x180