H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

B.5.12. Lower 4 bytes of the Destination address for Flow Control

Offset: 0x60D

Lower 4 bytes of the Destination address for Flow Control Fields

Bit Name Description Access Reset
31:0 daddrl Flow control Destination Address
Lower 4 bytes of the 6 byte destination address used for SFC and PFC frames
  • At power-on, daddrl is set to 32'hC2000001
  • After i_csr_rst_n is asserted, daddrl is set to the value given by module parameter tx_pause_daddr[31:0]
RW 0xC2000001