H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024
Public

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6.4. RX PCS Interface to User Logic

The H-Tile Hard IP for Ethernet IP core RX client interface in PCS Only variations employs the Media Independent Interface (MII) protocol.

The RX PCS acts as a source and the client acts as a sink in the receive direction.

Table 17.  Signals of the MII RX Client InterfaceAll interface signals are clocked by the i_clk_rx clock.

Signal Name

Description

i_clk_rx The RX clock for the IP core is i_clk_rx. The frequency of this clock is 402.83203125 MHz.

o_rx_mii_d[255:0]

RX MII data. Data is in MII encoding. o_rx_mii_d[7:0] holds the first byte the IP core received on the Ethernet link. o_rx_mii_d[0] holds the first bit the IP core received on the Ethernet link.

When o_rx_mii_valid has the value of 0 or o_rx_mii_am_valid has the value of 1, the value on o_rx_mii_d is invalid.

o_rx_mii_c[31:0]

RX MII control bits. Each bit corresponds to a byte of o_rx_mii_d. o_rx_mii_c[0] corresponds to o_rx_mii_d[7:0], o_rx_mii_c[1] corresponds to o_rx_mii_d[15:8], and so on.

If the value of a bit is 1, the corresponding data byte is a control byte. If the value of a bit is 0, the corresponding data byte is data.

The Start of Packet byte (0xFB), End of Packet byte (0xFD), Idle bytes (0x07), and error byte (0xFE) are control bytes, but the preamble bytes, Start of Frame (SFD) byte (0xD5), CRC bytes, and payload bytes are data bytes.

When o_rx_mii_valid has the value of 0 or o_rx_mii_am_valid has the value of 1, the value on o_rx_mii_c is invalid.

o_rx_mii_valid Indicates that o_rx_mii_d, o_rx_mii_c, and o_rx_mii_am_valid are valid.
o_rx_mii_am_valid Indicates the IP core received a valid alignment marker on the Ethernet link.

When o_rx_mii_valid has the value of 0, the value on o_rx_mii_am_valid is invalid. The value of o_rx_mii_valid may fall while the IP core is asserting o_rx_mii_am_valid.

Figure 27. RX MII Client Interface for H-Tile Hard IP for Ethernet IP Core