H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

B.2.11. RX PCS Status for AN/LT

Offset: 0x326

RX PCS Status for AN/LT Fields

Bit Name Description Access Reset
1 hi_ber Hi-BER

1: One or more virtual lanes are in the Hi-BER state defined in the Ethernet specification

RO 0x0
0 rx_aligned RX PCS fully aligned

1: The RX PCS is fully aligned and ready to start decoding data

RO 0x0